Entity: single_reg
Diagram
clk
[1:0]
RegWrite
reset
[31:0]
WriteData
[31:0]
ReadData
Description
Generics and ports
Table 1.1 Generics
Table 1.2 Ports
Port name
Direction
Type
Description
clk
input
RegWrite
input
[1:0]
reset
input
WriteData
input
[31:0]
ReadData
output
[31:0]