Entity: mux32_5

Diagram

[31:0] InputA [31:0] InputB [31:0] InputC [31:0] HI_reg [31:0] LO_reg [2:0] CtlSig [31:0] Output

Description

Generics and ports

Table 1.1 Generics

Table 1.2 Ports

Port name Direction Type Description
InputA input [31:0]
InputB input [31:0]
InputC input [31:0]
HI_reg input [31:0]
LO_reg input [31:0]
CtlSig input [2:0]
Output output [31:0]