Entity: mips_cpu_harvard

Diagram

clk reset clk_enable [31:0] instr_readdata [31:0] data_readdata active [31:0] register_v0 [31:0] instr_address [31:0] data_address data_write data_read [31:0] data_writedata

Description

Generics and ports

Table 1.1 Generics

Table 1.2 Ports

Port name Direction Type Description
clk input
reset input
active output
register_v0 output [31:0]
clk_enable input
instr_address output [31:0]
instr_readdata input [31:0]
data_address output [31:0]
data_write output
data_read output
data_writedata output [31:0]
data_readdata input [31:0]