Entity: delayslot

Diagram

clk Branch Jump JR [31:0] branch_address [31:0] jump_address [31:0] PCplus8 [31:0] rs_content [31:0] delay_addr

Description

Generics and ports

Table 1.1 Generics

Table 1.2 Ports

Port name Direction Type Description
clk input
Branch input
Jump input
JR input
branch_address input [31:0]
jump_address input [31:0]
PCplus8 input [31:0]
rs_content input [31:0]
delay_addr output [31:0]